1. Field
This disclosure generally relates to the field of semiconductor device packaging. More specifically, this disclosure relates to an ultra-small chip assembly and method for manufacturing an ultra-small chip assembly.
2. Related Art
As semiconductor devices continue to shrink in size, in order to reduce the overall device size after packaging, it is necessary to increase the volume ratio that is shared by chips in the package.
In traditional semiconductor devices, the chip or die is first affixed onto a support platform of the lead-wire frame of the chip package, and a set of electrodes on the die are then connected to a separate wire-bonding platform by lead wires. In such designs, the wire-bonding platform and the support platform of the lead-wire frame typically account for a lot of volume within the chip package. As a result, the volume ratio of the die within the chip package cannot be too high. These factors have hampered the miniaturization development trend of semiconductor devices. For example, FIG. 1 presents a diagram illustrating an existing ultra-small “QFN” chip package 100, which comprises a die 110, a lead frame 120, and a lead pin 130. A typical package size of such a structure is 0.62 mm×0.32 mm, but the size of die 100 itself is 0.2 mm×0.2 mm. In this design, a majority of the package volume is occupied by lead frame 120 and lead pin 130, while die 110 occupies only about 20% of the area. As the size of die 110 continues to decrease, the aforementioned ratio will be reduced further, due to the fact that the reduction in size of lead frame 120 and lead pin 130 is limited, but their portion of volume ratio will increase.